Haneul Park
HP

Haneul Park

Ph.D. Candidate, ECE @ UIUC · Intern @ SK Hynix · prev. Google Systems Research

My name, Haneul (하늘), means sky in Korean — fittingly, I spend my days in the clouds: I design processors and memory/network subsystems for datacenters. I am a Ph.D. candidate in Electrical and Computer Engineering at the University of Illinois Urbana-Champaign, advised by Prof. Nam Sung Kim, working on CXL tiered memory, LLC management for fast I/O, and the simulation tools to explore them.

  • CXL Memory
  • LLC & I/O
  • Datacenter Architecture
  • gem5
  • HW–SW Co-design
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ResearchPublications

MICRO2026To appear

Rethinking Compression for CXL Memory Expanders at Hyperscale

Haneul Park, Grant Ayers, Nam Sung Kim, Philip Levis, Brian Morris

The first performance exploration of the OCP CXL Tiered Memory Expander with inline compression, rethinking which compression algorithm and block size hyperscale expanders should adopt. Full-length follow-up to our CAL letter.

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IEEE CAL2026

Capacity–Latency Tradeoffs in CXL Memory Expanders at Hyperscale

Haneul Park, Grant Ayers, Nam Sung Kim, Philip Levis, Brian Morris

Counter-intuitively, a slower and more complex compression algorithm can make a CXL memory expander both bigger and faster — the DRAM traffic it saves outweighs the decompression time it adds.

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ISPASS2026Best Paper Nomination

Compiler and System Optimizations for gem5 Simulator

Haneul Park*, Siddharth Agarwal*, Pradyun Narkadamilli, Kiung Jung, Yongjun Park, Ipoom Jeong, Nam Sung Kim (*equal contribution)

A universal PGO profile and system-level tuning make gem5 17% faster per simulation and 27% higher in aggregate throughput — without touching simulation results.

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ISCA2025

A4: Microarchitecture-Aware LLC Management for Datacenter Servers with Emerging I/O Devices

Haneul Park, Jiaqi Lou, Sangjin Lee, Yifan Yuan, Kyoung Soo Park, Yongseok Son, Ipoom Jeong, Nam Sung Kim

High-speed I/O devices and CPU cores fight over the last-level cache in ways the ISA can't see. A4 finds the microarchitectural culprits and manages around them, speeding up high-priority workloads by 51%.

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ISCA2023

DRAM Translation Layer: Software-Transparent DRAM Power Savings for Disaggregated Memory

Wenjing Jin, Wonsuk Jang, Haneul Park, Jongsung Lee, Soosung Kim, Jae W. Lee

An address translation layer for CXL memory pools that coalesces cold and unallocated regions, unlocking rank-level DRAM power-down with zero software changes.

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