Haneul Park
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ISCA2023

DRAM Translation Layer: Software-Transparent DRAM Power Savings for Disaggregated Memory

Wenjing Jin, Wonsuk Jang, Haneul Park, Jongsung Lee, Soosung Kim, Jae W. Lee

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Host A Host B DRAM Translation Layer coalesce cold + unallocated remap CXL memory pool Rank 0 Rank 1 Rank 2 Rank 3 Rank 4 Rank 5 cold ranks → power-down

By remapping addresses below the OS, cold and unallocated memory coalesces onto a few ranks — which can then be powered down without any software changes.

TL;DR

An address translation layer for CXL-based memory pools that coalesces unallocated and cold memory regions, enabling rank-level DRAM power-down — completely transparent to software.

Why it matters

DRAM accounts for roughly 40% of total system power in datacenter servers, and memory disaggregation — pooling DRAM across hosts for utilization — only raises the stakes. Average DRAM utilization in today's datacenters is low, so putting unallocated and cold ranks into a power-saving mode is appealing. But conventional fine-grained address interleaving, designed to maximize rank-level parallelism, scatters every page across all ranks — exactly the wrong layout for powering any of them down.

Key idea

Insert a thin address translation layer inside the memory pool, below the OS. By remapping device addresses, unallocated and cold regions are coalesced onto as few ranks as possible; those ranks then enter power-down. No host software, OS, or application changes are required.

This work started during my undergraduate research at SNU's Architecture and Code Optimization Lab with Prof. Jae W. Lee, and appeared at ISCA 2023.

BibTeX

@inproceedings{jin2023dtl,
  author    = {Wenjing Jin and Wonsuk Jang and Haneul Park and Jongsung Lee
               and Soosung Kim and Jae W. Lee},
  title     = {{DRAM} Translation Layer: Software-Transparent {DRAM} Power
               Savings for Disaggregated Memory},
  booktitle = {Proceedings of the 50th Annual International Symposium on
               Computer Architecture (ISCA)},
  year      = {2023}
}