Capacity–Latency Tradeoffs in CXL Memory Expander at Hyperscale
Conventional wisdom treats compression as a capacity–latency trade — this paper shows the right algorithm and block size can deliver both. (Illustrative diagram; replace with the paper's figure.)
In a CXL memory expander with inline compression, a slower but stronger compression algorithm can simultaneously increase capacity and reduce access latency: the DRAM traffic it saves more than offsets the extra decompression time.
Why it matters
DRAM dominates the cost of hyperscale datacenter servers, and AI-driven memory supply shortages are pushing costs even higher. CXL memory expanders cut server cost by reusing legacy DDR modules from older servers, and inline compression stretches their effective capacity further — but every compressed byte is normally assumed to cost access latency.
Key findings
- We investigate two critical expander design points — the compression algorithm and the compression block size — using a compressibility benchmark and the latest cold-memory access traces from a hyperscaler.
- Current commercial devices default to simple, fast compression on 4 kB blocks. Switching to a stronger algorithm (Zstd) simultaneously increases capacity by ~30% and reduces latency by ~12%.
- The insight is counter-intuitive: because decompression sits on the critical path, conventional wisdom prefers fast algorithms — but memory bandwidth and queueing dominate end-to-end latency, so the reduced read amplification of stronger compression wins.
This work was done during my student researcher role in Google's Systems Research Group, and suggests future expander specifications should be designed differently.
BibTeX
@article{park2026cxl,
author = {Haneul Park and Grant Ayers and Nam Sung Kim and Philip Levis
and Brian Morris},
title = {Capacity-Latency Tradeoffs in {CXL} Memory Expander at Hyperscale},
journal = {IEEE Computer Architecture Letters},
volume = {25},
year = {2026}
}