Rethinking Compression for CXL Memory Expanders at Hyperscale
Every 64-byte read decompresses a whole block — so the algorithm and block size decide both how much DRAM traffic each access generates and how long decompression takes. (Illustrative diagram; replace with the paper's figure.)
Commercial CXL memory expanders default to fast, weak compression to keep decompression off the critical path. At hyperscale that is the wrong call: memory bandwidth and queueing dominate end-to-end latency, so a slower but stronger algorithm makes the expander both bigger and faster.
Why it matters
DRAM dominates the cost of hyperscale datacenter servers, and AI-driven memory supply shortages keep pushing costs higher. The OCP CXL Tiered Memory Expander cuts server cost by reusing legacy DDR modules, and inline compression stretches effective capacity further — but its compression design points were set by conventional wisdom, not measurement.
What's in the paper
- The first performance exploration of the OCP CXL Tiered Memory Expander with inline compression, analyzing and quantifying capacity–latency tradeoffs at hyperscale.
- A production-representative benchmark for cold-memory access patterns, built from the latest cold-memory traces of a hyperscaler, for evaluating tiered memory systems.
- A sweep of the two critical design points — compression algorithm and compression block size — showing that switching from the fast default to a stronger algorithm (Zstd) simultaneously increases capacity by ~30% and reduces latency by ~12%.
- The mechanism: decompression time grows, but the reduced read amplification saves more DRAM bandwidth and queueing delay than the decompressor adds — motivating different choices in future expander specifications.
This work was done during my student researcher role in Google's Systems Research Group. An early letter version appeared in IEEE Computer Architecture Letters.
BibTeX
@inproceedings{park2026rethinking,
author = {Haneul Park and Grant Ayers and Nam Sung Kim and Philip Levis
and Brian Morris},
title = {Rethinking Compression for {CXL} Memory Expanders at Hyperscale},
booktitle = {IEEE/ACM International Symposium on Microarchitecture (MICRO)},
year = {2026}
}